JPH0478840U - - Google Patents
Info
- Publication number
- JPH0478840U JPH0478840U JP12285790U JP12285790U JPH0478840U JP H0478840 U JPH0478840 U JP H0478840U JP 12285790 U JP12285790 U JP 12285790U JP 12285790 U JP12285790 U JP 12285790U JP H0478840 U JPH0478840 U JP H0478840U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- clock
- loop
- signal generator
- pll
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12285790U JPH0478840U (en]) | 1990-11-21 | 1990-11-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12285790U JPH0478840U (en]) | 1990-11-21 | 1990-11-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0478840U true JPH0478840U (en]) | 1992-07-09 |
Family
ID=31870600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12285790U Pending JPH0478840U (en]) | 1990-11-21 | 1990-11-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0478840U (en]) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004040835A1 (ja) * | 2002-11-01 | 2004-05-13 | Fujitsu Limited | データ処理回路 |
-
1990
- 1990-11-21 JP JP12285790U patent/JPH0478840U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004040835A1 (ja) * | 2002-11-01 | 2004-05-13 | Fujitsu Limited | データ処理回路 |
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